Integrated semiconductor memory devices must be capable of high speed operation. To improve the overall speed of memory devices, a bit line precharge circuit is conventionally used to produce a desired voltage level on bit lines prior to a write or read operation. By first producing a desired voltage level on bit lines, the speed of a memory device may be maximized during read or write operations.
FIG. 1 shows a conventional RAM circuit 10, including a conventional MOS static RAM cell 12 coupled between a bit line pair BL1 14 and BL2 16, and coupled to word line WL 18. RAM cell 12 includes a resistor 20 and an NMOS transistor 22 coupled in series to form the first inverter of the memory cell 12, and a second resistor 24 and a second NMOS transistor 26 coupled in series to form the remaining inverter. These two inverters are connected in a positive feedback fashion to create a latching circuit. Two transistors, NMOS transistor 28 and NMOS transistor 30, serve as transmission gates or pass transistors connecting the latching circuit to bit line pair BL1 14 and BL2 16, respectively. The gates of transistors 28 and 30 are connected to word line WL 18.
Typically, a RAM device 10 will have many memory cells 12 disposed in parallel between bit lines BL1 14 and BL2 16. The number of memory cells, however, contribute to a relatively large capacitive loading on bit lines BL1 14 and BL2 16. The capacitive loading on the bit lines create read and write disturb problems. Read and write disturb problems occur when the pass transistors 28 and 30 are activated to couple the latching circuit to the bit lines BL1 14 and BL2 16. If the capacitance on either bit line BL1 14 or BL2 16 is large enough, the data latched in the RAM cell 12 may be altered during reading of that RAM cell, i.e., a read disturb problem. Alternatively, random data can be unintentionally written into RAM cell 12 when another RAM cell (not shown) that is on word line 18 is in a write cycle, i.e., a write disturb problem. Thus, prior to activating transistor 28 and 30, precharge circuits are used to equalize and regulate the voltage on the bit lines BL1 14 and BL2 16 to prevent read or write disturb problems.
Thus, RAM circuit 10 includes conventional precharge circuits 40, 41 coupled to bit lines BL1 14 and BL2 16, respectively, and an NMOS transistor 47 coupled between bit lines BL1 14 and BL2 16. As shown, precharge circuits 40, 41 use two NMOS transistors 42, 44 and 43, 45, respectively, in a voltage divider configuration between a voltage source Vcc and ground. When precharge circuits 40, 41 and transistor 47 receive a precharge signal PCH, which is asserted on the gates of NMOS transistors 42, 44 and 43, 45, precharge circuits 40, 41 provide a precharge voltage level on bit lines BL1 14 and BL2 16. Precharge circuits 40, 41 precharge bit lines BL1 14 and BL2 16 to a voltage level that is some portion of Vcc, e.g., 1/2 Vcc. By applying the desired precharge voltage level on bit lines BL1 14 and BL2 16, the read reliability and switching time for a read operation are greatly improved.
Unfortunately, precharge circuits 40, 41 and a sense amplifier (not shown) that conventionally reads BL1 14 and BL2 16 draw substantial current during the precharge operation, which creates a current spike. Typically, RAM device 10 includes many pairs of bit lines, each of which is precharged. Consequently, the total amount of power consumed using conventional precharge circuit is large.